1. Field of the Invention
The invention generally relates to testing memory devices and, more particularly, to devices and techniques that allow the detection of floating word lines in dynamic random access memory (DRAM) devices.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices.
Such devices utilize memory cells (also referred to as storage nodes) typically consisting of one transistor and one capacitor. The cells are accessed by activating a word line, switching on the transistor and coupling the capacitor to a bit line. The stored charge on the capacitor is then sensed by a sense amplifier to determine if a logical ‘1’ or ‘0’ is stored in the accessed cell. To optimize access to cells (e.g., to speed access, simplify signal routing, and/or facilitate layout), word lines are sometimes grouped and controlled by master word lines. Individual word lines in a group (referred to as local word lines to distinguish them from master word lines) are activated by a) activating the controlling master word line for the group and b) asserting a drive line for a particular word line.
FIG. 1 shows a portion of a conventional array structure 100, utilizing groups of word lines 102 controlled by master word lines 110, to access memory cells 107, in a standby mode. Illustratively, each master word line 110 controls four (4) local word lines 102. In the illustrated standby mode, word line (WL) reset lines 124 are activated (as indicated by bold lines), thereby pulling each connected word line 102 down to a low (or negative) word line voltage level (VNWLL) via pull down transistors 114. This keeps the cell transistors connected to the word lines 102 closed, thereby maintaining the information as stored charge in the cell capacitors.
FIG. 2 shows the same array portion as FIG. 1, but this time in an active mode with the left most master word line group (group 0) selected, as indicated by the bold border for the corresponding master word line 110. Illustratively, the word line 0 drive line 122 (WL Drive 0) is pulled up (as indicated by the bold line) to a word line high voltage (VPP) and in each word line group, the corresponding pull up transistor 112 is connected to VPP.
Only in the selected master word line group (group 0 in this example) the pull up transistor 112 is activated, thereby connecting the corresponding local word line 102 to VPP, via the drive line 122 (as indicated by the bold line). This causes the cell transistor of the corresponding memory cell 107 to be switched on, thereby connecting the cell transistor to the bit line 103. As a result, information can be read from or written to the memory cell 107 via the bit line (BL) 103, by a sense amplifier 104. In a similar manner, information can be read from or written to the other memory cells 107 via the same bit line, as well as complementary bit line (/BL) 103 by activating other master word lines 110 and drive lines 122.
In the illustrated example, the local word lines 102 are driven only from one side. Unfortunately, this single sided concept has the disadvantage that as soon as the drive voltage is removed from this drive side, the local word lines are not driven any more and may float at an undefined level.
Simulations have shown that the critical voltage range for a “floating word line” is currently in the range of 1.3V to 1.6V. In this range, it has been observed that memory cells connected to floating word lines can destroy information stored in good word line connected cells (e.g., by remaining connected to bit lines), leading to read failures. Analysis has shown that typically only word lines which remain pulled up somewhat, for example, due to lack of a pull down connection due to a defect (region 130 shown in FIG. 2), generate application relevant problems. Actual floating word lines which are not connected to anything seem not to cause these problems. Unfortunately, in current designs utilizing drive lines driven from one side, it is difficult to drive a word line to a defined intermediate VPP level and test for this floating word line condition fast enough (e.g., before this level is lost).
Therefore, there has not been a reliable method to identify chips which are affected by this floating word line problem, e.g., at wafer test. Accordingly, what is needed are apparatus and methods that allow testing to identify chips having floating word lines that cause read failures.